ttnn.bitwise_left_shift

ttnn.bitwise_left_shift = FastOperation(python_fully_qualified_name='ttnn.bitwise_left_shift', function=<ttnn._ttnn.operations.binary.bitwise_left_shift_t object>, preprocess_golden_function_inputs=<function default_preprocess_golden_function_inputs>, golden_function=<function _golden_function_bitwise_left_shift>, postprocess_golden_function_outputs=<function default_postprocess_golden_function_outputs>, is_cpp_operation=True, is_experimental=False)

Perform bitwise_left_shift operation on input_tensor_a by input_tensor_b and returns the tensor with the same layout as input_tensor_a. input_tensor_b has shift_bits which are integers within range (0, 31)

\[\mathrm{{output\_tensor}}_i = \verb|bitwise_and|(\mathrm{{input\_tensor\_a, input\_tensor\_b}})\]
Parameters:

  • input_tensor_a (ttnn.Tensor) – the input tensor.

  • input_tensor_b (ttnn.Tensor or Integer) – the input tensor.

Keyword Arguments:

  • memory_config (ttnn.MemoryConfig, optional) – memory configuration for the operation. Defaults to None.

  • output_tensor (ttnn.Tensor, optional) – preallocated output tensor. Defaults to None.

  • sub_core_grids (ttnn.CoreRangeSet, optional) – restrict execution to a subset of cores (e.g. for subdevice use). Defaults to None.

  • sub_device_id (ttnn.SubDeviceId, optional) – sub device ID — the op resolves cores internally. Mutually exclusive with sub_core_grids. Defaults to None.

Returns:

ttnn.Tensor – the output tensor.

Binary elementwise operations, C=op(A,B), support input tensors A and B in row major and tile layout, in interleaved or sharded format (height, width or block sharded), in DRAM or L1. A and B are completely independent, and can have different tensor specs.

Broadcast of A and B operands is supported up to dimension 5 (DNCHW). Any dimensions of size 1 in either A or B will be expanded to match the other input, and data will be duplicated along that dimension. For example, if the shape of A is [2,1,1,32] and B is [1,16,8,1], the output shape will be [2,16,8,32]. The size of dimensions higher than 5 must match between A and B.

The output C also supports row major and tile layout, interleaved or sharded format (height, width or block sharded), in DRAM or L1. The tensor spec of C is independent of A and B, and can be explicitly set using the optional output tensor input; if not provided, the operation will attempt a best decision at an appropriate tensor spec. The dimensions of C, or equivalently the optional output tensor, must match the broadcast-matched size of A and B.

Performance considerations: Elementwise operations operate natively in tile format, tiled tensors are preferred as an input, and row-major tensors are tilized and untilized during the operation. L1 sharded layout is preferred, with no broadcast and matching tensor specs for A, B and C.

Note

Supported dtypes and layouts:

Dtypes

Layouts

INT32, UINT32, UINT16

TILE, ROW_MAJOR

If the input tensor is ROW_MAJOR layout, it will be internally converted to TILE layout.