Advanced Topics

This section provides an overview of the details of the Tensix architecture and how Metalium integrates with it. The documents here are intended for developers looking to understand the underlying hardware and software interactions.

Hardware implications and the effects

• Tiles
  • Internal structure of a Tile
  • Conversion between tiles and row-major format
• Memory from a kernel developer’s perspective
  • Data addressing on Tenstorrent processors
    • RISC-V Address Space
    • DRAM tiles
    • Memory access via the NoC
  • Tensor Layout
  • Memory placement
    • Lock step allocation
    • Interleaved memory
    • SRAM buffers
    • Sharded tensor
• Compute Engines and Data Flow within Tensix
  • Component introduction
  • Dst register
  • Matrix engine/FPU
  • Vector engine/SFPU
• Achieving FP32 Accuracy for Computation
  • Host-Side Configuration
  • Kernel-Side Implementation
  • Distinguishing Between matrix and vector engine APIs